Infineon Aurix: How to allocate trace buffer for tracing?

First check, whether your CPU supports trace - refer to the topic Trace is not licensed.

Possible solutions

Trace Buffer is configured in Hardware / CPU Options / SoC:

Default

The option Use all available memory for trace buffer should work in most cases assuming that complete TCM memory is available for Trace.

TCM

When a limited amount of TCM memory or Tiles are available for Trace (the rest is used for Calibration):

• Uncheck Use all available memory for trace buffer option.
• Select TCM from the drop-down menu.
• Note that the Trace buffer can consist of consecutive Tiles only. Define the First tile and define the Number of tiles available for trace.

XTM

When whole TCM memory is used for Calibration and the Emulation Device provides optional XTM memory, which is available for trace:

• Uncheck Use all available memory for trace buffer option.
• Select XTM from the drop-down menu.
• Note that Trace buffer can consists of consecutive Tiles only. Define the First tile and define Number of tiles available for trace.

LMU

See more information in winIDEA Help.

Short explanation

TC2xx and TC3xx

Trace data is stored in the so-called Emulation Memory (EMEM). By default, Emulation Memory consists of a regular memory array (TCM – Trace Calibration Memory) built out of RAM Blocks (Tiles), which can be split into a Trace memory and a Calibration memory part. Additionally, certain Emulation Devices (ED) offer the optional memory XTM (Extended Trace Memory) for Trace. XTM can be also assigned to Calibration. If the Emulation Device with AGBT has TCM or XTM assigned to Trace, TCM Tile0 or XTM Tile0 acts as an AGBT Trace buffer.

TC4xx

Trace data is stored (typically) in a Local Memory Unit (LMU). LMU has flat address space that is divided into several regions - the actual number of them depends on the specific device. In most cases, winIDEA can automatically configure the LMU.

More resources

• Infineon AURIX winIDEA Configuration - Tutorial, pages 8-9 
• Trace Data Storage & Output at 35:40  - Webinar Trace Explained
• SoC chapter - winIDEA Help