1. Change the hardware:
2.1 Verify, if a signal PORST’ is always low. The reason could be faulty target or Debug Adapter (refer to the first solution) or active watchdog which holds the signal to logic low level.
The start of emulation on TriCore DAP. Trigger is set to the positive edge on RESET. After reset DAP communication goes via two lines (DAP0 and DAP1). It switches to 3 pin mode if DAP Wide is selected.
DAP protocol is a message based protocol. Debugger sends command (telegram) and ECU answers to command at the same line.
Zoomed recording when reset is released.
Zoomed recording when first DAP telegram is sent. First telegram is SYNC telegram where ECU answer with 0xAAAAAAAA (See the 10101010101010101 stream).
2.2 Bent pin on the DTM connector (In most cases that is the pin 40 on ST1 connector). Bent pin disables connection between the debugger and the Target or causes a short-circuit with the pin 38 which is usually most of the time low.
3. Bad contact between CPU and the socket:
4. Disable internal and external watchdogs. winIDEA is using a FLASH monitor which is used to program FLASH during download operation. Debugger first initializes part of the target RAM where monitor will be placed, then downloads monitor and execute it. If external watchdog is triggered it causes CPU to reset which invalidates RAM and flash monitor stops working and hence error message displayed by the debugger.
4.1. Refer to the solution 2.1 of this topic.
4.2 Inspect the schematics of the target and make sure you are not using any external watchdog chip (e.g. Infineon TLE9278QX, TLE7368, TLF35584, NXP UJA113X). Follow the example below.
Example: Emulator’s signal PORST’ is an open drain with 1K Ohm pull-up resistor which can be pulled down by the external watchdog chip. CPU behaves as a multiple output system power supply and when the watchdog is enabled, this chip expects that it is disabled in ~600ms after power on reset. If it is not disabled, it resets the TriCore chip. After that multiple output system power supply is turned off and hence cuts the power to the TriCore chip.
Note: That sequence must be executed before 600ms expires (that is time after after target power on and not after reset). It initializes SPI in TriCore chip and via SPI communication disables watchdog in the TLF chip.
5. Please refer to the Infineon’s documentation for detailed information which Debug Mode (Standard, Wide) is supported.
6. Make sure that selection in winIDEA (Hardware menu / CPU Options / SoC tab) corresponds with the actual logic levels on TRST’ pin during power on reset. It is recommended to connect the TRST' pin:
Note: Signal TRST’ (previously DAPEN) is used to select either DAP or JTAG on power on reset. It is important which logic level is present on the TRST' pin during power on reset sequence: if logic 0 - JTAG is selected; if logic 1 - DAP is selected.
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