By default the fast internal RC oscillator (FIRC) is used for generating the trace clock. The resistor and capacitor values (RC components) of this oscillator show significant tolerances due to the nature of the manufacturing process and also vary upon differences in supplied voltage and working temperature. The resulting trace clock frequency can vary to such an extent that it causes bit errors in the trace messages which the trace analyzer can no longer properly decode.
Reducing the trace clock frequency makes the trace recording less susceptible to errors caused by frequency variations.
1. Go to Hardware / CPU options / Analyzer.
2. At SoC Initialization, Before start select Custom.
3. Click the arrow symbol next to the Scripts field and choose S32K34x_TraceInit.cpp.
4. Once again click the arrow symbol to select Parameters for S32K34x_TraceInit.cpp. In the dialog that opens, select a higher value for the TraceClkDiv property.
4. Restart the debug session and perform a trace line calibration before running the Analyzer.
If the first solution doesn't provide the required trace bandwidth, the source of the trace clock needs to be switched to a more stable external clock (FXOSC).
1. Initialize the FXOSC and PLL's in your application and set up either PHI0 or PHI1 as the trace clock source.
2. In the trace initialization script options, change the TraceClkSrc accordingly.
3. Restart the debug session and perform a trace line calibration.
Sorry this article didn't answer your question, we'd love to hear how we can improve it.
Note: This form won't submit a case. We'll just use it to make this article better.