When Aurix devices are in the debug mode, Watchdog is by default enabled, but the Watchdog Timer is unconditionally suspended (stopped), which means that the Watchdog never resets the chip.
To use the Watchdog during debugging, you have to disable the Watchdog Timer suspended logic (or enable the Watchdog timer).
To enable the Watchdog Timer you have to set WDTSUS (Watchdog Timer Suspension Control) in the CBS_OCNTRL register. In this case, the Watchdog Timer suspend mode is controlled by the TL1 line.
1. Configure multi-core synchronization by enabling the checkbox in Hardware / CPU Options / Debugging / Synchronize selected cores when possible.
2. (optional) Remove some cores from synchronization in the same window under Cores / <CoreName>.
2. Create a new INI script and add it to the Initialize fields in Hardware / CPU Options / Reset:
The script should contain the following line:
A CBS_OCNTRL L 0x00003000 //Sets WDTSUS
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