When AURIX devices are in the debug mode, Watchdog is by default enabled, but the Watchdog Timer is unconditionally suspended (stopped), which means that the Watchdog never resets the chip.
To use the Watchdog during debugging, you have to disable the Watchdog Timer suspended logic (or enable the Watchdog timer).
To enable the Watchdog Timer you have to set WDTSUS (Watchdog Timer Suspension Control) in the CBS_OCNTRL register. In this case Watchdog Timer suspend mode is controlled by the TL1 line.
First configure the TL1 and after set the WDTSUS.
1. Open a multi-core synchronization script, which is distributed with winIDEA.
2. Adjust the script and add the following line after the TL1.
A CBS_OCNTRL L 0x00003000 //Sets WDTSUS
3. Save it and load it to Hardware menu / CPU Options / Reset / Initialize / Initialize before Debug session section. Now the Watchdog Timer is not unconditionally suspended (stopped), but suspended when the TL1 line is in 1.
By default TL1 isn't configured as a suspend line, but it can be used as such for all the cores, timers, CAN, LIN, Flexray, DMA and optionally for watchdog as well.
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