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How to configure maximum debug interface frequency for best debug performance?


Maximum debug interface frequency ensures that under all circumstances the debug interface communication works reliably, which is especially important during FLASH programming, where in worst case an error in transmission could cause the CPU/SoC device failure.

Higher debug interface frequency brings shorter FLASH programming times while regular debugging experience using run/step/stop control and available debug windows might not be affected noticeably by increasing the debug interface frequency.

Programming special regions of FLASH with an unstable debug clock can lock the chip.

Possible solution:

Use a Python script.

Refer to the topic How to find maximum debug frequency.

Manual approach

Before you program the device flash you have to test if a debug session is stable. 

1. Open Hardware menu / CPU Options / SoC

2. Steadily increase the debug clock to determine the max value.

3. Perform the following actions:

  • Step through the code and see if it works reliably.
  • Perform reading RAM via Memory Window.

With certain CPUs/SoCs, RAM must be initialized before you can use it and ECC (Error-Correction Code) protection must be disabled (or else "??" will be shown in the Memory Window). Refer to CPU/SoC Reference Manual for more details on RAM usage and operation.

Real-time memory updates should be enabled for this particular test and RAM data values shouldn't change. If the values do change, it means that each time a different value is read. That usually indicates an unstable debug connection. Don't forget to disable real-time memory updates for the memory window after the tests are completed.

3.3. Observing FLASH via Memory Window (if the code is already programmed into the FLASH).

Note that the FLASH data shouldn't change while scrolling down and up in the FLASH address range.

4. Repeat steps 1 - 3 until you find a maximum debug interface frequency, which still works. 

5. Once you reach the highest clock at which all of the above tests pass, reduce the debug clock by 10%. This adds safety margin which ensures that under all circumstances the debug interface communication will work reliably.

More resources:

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