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NXP/ST Power Architecture / SPC58: Accessing Performance Monitor Registers (PMR)

03-Aug-2021

Before accessing the Performance Monitor Registers (PMR) both Internal Debug Mode (IDM) and Performance Monitor Interrupt (PMI) bits must be set in the External Debug Resource Allocation Control (EDBRAC0) register. See the EDBRAC0 register structure below:


The default value for EDBRAC0 register is 0x180 (bits PMI and MPU set). 


Possible solution:

To be able to write to PMR, you have to set the IDM bit:

1. Open Hardware menu / CPU Options / <Core>.

2. Type in the JTAG debug select field value 0x40000180. This can be done for each core. 




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