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Infineon Aurix TC4x: How to enable debug access for PPU Core?

18-Mar-2024

After a reset, the debug access to the PPU core is blocked due to the safety level ASIL-C of PPU Safety Mechanism Control Register (Bitfield SAFETYL in PPUC_SMCTRL). To get access to the PPU core the register has to be changed to QM Level. During a debug session with lots of resets, the change via the SFR register can be annoying over time. To avoid this an INI script (.ini) which is invoked after every reset can be very helpful.


Solution

The INI script can be invoked in Hardware / CPU Options / Reset:



Content of INI-script:

//Enable Debug Access for PPU core
A PPUC_CLC L 0 //Enable PPU Clock
A PPUC_SMCTRL L 0 //Set PPU Safety Mechanism Control Register to QM Level
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