TriCore architecturally does not have a mechanism that would allow CPU to be stopped when a trap (in some other architectures known as an exception) occurs. There are many mechanisms that could cause a core to trap, i.e. null pointer dereference, data alignment error, etc.
However, with a bit of knowledge of the inner workings, it is possible to achieve the same behaviour through hardware breakpoints.
TriCore trap table address is written in the BTV register. Its value can be obtained with the help of the SFR Window. In this case, the start of the trap table is on the address 0xA0000000.
1. Open the SFR Window and locate the address.
2. Configure range execution breakpoint through Debug menu / Hardware Breakpoints.
In the case of TriCore TC1.6.2, this trap is Internal Protection Trap - Memory Protection Null Address. For other traps consult Infineon TriCore documentation.
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