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Infineon AURIX: How to configure general CPU settings?


These configuration steps are required to connect iSYSTEM BlueBox to the Target and perform CPU Reset command, which establishes initial Debug connection.


1. Select your Device in a new Workspace

2. Configure SoC settings. 

TriCore/AURIX devices can feature:

  • JTAG debug interface,
  • DAP Standard debug interface - uses one clock (DAP0) and one bidirectional data (DAP1) line,
  • DAP Wide debug interface - uses one clock (DAP0) and two bidirectional data (DAP1 and DAP2) lines. 

Some devices feature both JTAG and DAP debug interfaces. In general the DAP debug interface is the preferred choice since it uses less physical pins and has higher data bandwidth.

1. Identify which debug interface provides the target debug connector on your target board. 

2. Select JTAG or DAP Standard or DAP Wide in the CPU Setup / SoC tab under the  Debug channel Mode.  Default DAP clock setting should work in most cases.

3. If JTAG debug protocol is selected, the JTAG scan speed is set in the JTAG tab, which is visible only when the JTAG debug protocol is selected and confirmed. 

3. Configure JTAG settings.

4. Password protection:
Certain TriCore devices provide a 256-bit password for debug interface protection to prevent unauthorized access to the TriCore on-chip debugging resources. Use option under the Hardware menu / CPU Options / SoC tab / Use Password when debug interface protection on the microcontroller is used. Use the debug interface protection with caution since the device can unintentionally become inaccessible.

More resources:

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