To execute and load an application to DDR RAM memory on Xilinx Zynq UltraScale+, DDR RAM memory needs to be properly initialized. In a regular or a production boot procedure, such initialization is usually done by one of the early-stage bootloaders. An example of such a bootloader for Xilinx Zynq UltraScale+ is the First Stage Bootloader (FSBL).
winIDEA can initialize DDR RAM memory by running a specified bootloader in SoC’ OCM RAM memory with an initialization script which is distributed with winIDEA in the SFR folder.
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