To execute and load an application to DDR RAM on Xilinx Zynq UltraScale+, DDR RAM needs to be correctly initialized. In a regular or a production boot procedure, such initialization is usually done by one of the early-stage bootloaders. An example of such a bootloader for Xilinx Zynq UltraScale+ is the First Stage Bootloader (FSBL).
winIDEA can initialize DDR RAM by running a specified bootloader in SoC’
OCM RAM with an initialization script distributed with winIDEA in the SFR
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